VLSI

Tattva have opened a VLSI front-end training program for fresher and Last year students of B.E./B.Tech in EEE/ECE/IT/CSE and M.E./M.Tech./MS/Msc in VLSI/electronics/computer science who wants to set his/her skills in cutting edge technology.

Interested candidate can send us resume on tattvainfonandha@gamil.com

The Training and Internship program consists in modules.The modules are: Training & Industrial standard Projects. In the training module trainees will get training on Digital Design, Verilog HDL, System Verilog, Universal Verification Methodology (UVM), python,Perl,Tcl, Linux, Projects.

During your training session, we will conduct expert lectures from various reputed institution as well as reputed companies.

Duration: 5– 6 Months

Note : This is paid project training program*

Note : We are offering the Online/Offline and Weekend Class for Demo contact us :7899433231/8884608550

VLSI

    Introduction To VLSI
  • Introduction to VLSI Design
  • ASIC Vs FPGA
  • RTL Design Methodologies
  • Introduction to ASIC Verification Methodologies
  • VLSI Design Flow steps demo
  • Advanced Digital Design
  • Introduction to Digital Electronics
  • Number System
  • Codes
  • Arithmetic Circuits
  • K-map Circuits and implementations
  • Combinational CircuitsDesign & Analysis
  • Latches & Flip-Flops
  • Shift Registers & Counters
  • Sequential CircuitsDesign and Analysis
  • HDL
  • Introduction to HDL
    • 1. Need of HDL
    • b. Features of HDL and Structural Coding
    • Bottom-Up and Top-Down Design Flows
    • d. Logic Circuit examples
    • e. Combinatorial Circuit Design and Coding (Both DUT and TB)
    • f. VHDL vs Verilog
  • Introduction to Verilog
    • a. Understand Verilog basics and Terminology
    • b. How Verilog used for Digital Design
    • c. How to write RTL using Verilog
    • d. Usage of Software’s – ModelSim and Xilinx
    • e. Simulation and Debugging of digital circuits
    • g. Knowing advanced Verilog Constructs
  • RTL Coding
    • a. Sequential circuits
    • b. Arithmetic, Logic, Equality, Relational, Bitwise,
    • c. Reduction
  • State Machines
    • a. Mealy/Moore State machines
    • b. Conditional compilation
    • c. Blocking and Non-blocking
    • d. Intra and Inter delays
    • e. Delay modeling (specify blocks)
  • Assignments/Examples
  • State Machine
    • a. Arbiter
    • b. FIFO
    • c. Coding DUT and Testbench
  • TestBenches
    • a. More Emphasis on Testplan
    • b. Creating Self-Checking TestBenches
    • c. Regressions
    • d. Debugging Functionality mistakes
    • e. Gate Level Simulation& Synthesis
  • Static timing analysis
  • What is the timing analysis
  • Types of TA
  • DTA
  • STA
  • Clock
  • Timing Parameters in STA
  • STA Procedure
  • Timing examples & solutions
  • Methods to improve timings
  • False paths
  • Multi-cycle paths
  • STA in pre-layout and post-layout of design
  • Industrial Project on Verilog
  • Industrial project design using Verilog coding (Router)
  • Introduction to VLSI & LINUX
  • Components of UNIX systems
  • Directory Structure
  • Utilities & Commands
  • Vi Editor
  • Introduction to SystemVerilog
  • Abstract modeling constructs
  • Arrays and its operators
  • SV scheduling semantics
  • SV scheduling semantics
  • Interface
  • Class
    • a. OOP
    • b. cast
    • c. inheritance
    • d. polymorphism
    • e. parameterization
  • Program construct
  • Final block
  • Enhanced Concurrency modeling
  • Inter process communication
  • Random vs. directed testing
  • Need for random testing
  • Constraints in SVTB
  • Class constraints
  • Randomize success / fail
  • Inheritance
  • Randomize.with()
  • Distribution
  • Function calls in constraints
  • Array constraints
  • Pre / post randomize
  • VERIFICATION METHODOLOGIES
  • UVM
  • Classes & OOP – Refreshs
  • DUT description
  • Overall view of UVM base classes, structure (UML diagrams)
  • UVM macros – need, basic usage
  • Unified messaging in UVM
  • Modeling Transactions
  • Modeling Transactors
  • Transaction Generator (uvm_sequencer)
  • UVM Phases
  • UVM agents (uvm_agent)
  • Modeling Environment (uvm_env)
  • Creating test cases (uvm_test
  • Putting it all togethe
  • Analysis Ports in UVM
  • Analysis FIFO
  • Building Monitor (uvm_monitor)
  • Checker (uvm_subscriber, uvm_analysis_imp)
  • Configurations in UVM
  • Advanced stimulus generation
  • ASSERTION BASED VERIFICATION
  • Introduction to Assertions & ABV
  • Types of assertions
    • Immediate
    • Concurrent
  • Boolean Expression
    • Sequence
    • Disable_iff
  • Verification Directives
    • Assert
    • Assume
    • Cover
    • Expect
  • Clock
  • Sequences (Declaration/structure)
  • Properties
  • Advanced topics
  • Clock
  • VIP development using UVM & System Verilog
  • Academic VIP development using UVM Methodology and System Verilog for AMBA , AHP.
  • BASIC CMOS CONCEPT